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SDCC ignorance

Posted by Adrian Bowyer 
SDCC ignorance
June 30, 2007 01:43PM
I'm just adding a ring buffer to the stepper firmware, so it always has a new line to plot ready and waiting when it finishes the last one (hence no comms pause while it gets the next).

It compiles fine, but I get a mysterious:

Expected bank 0 for r0x4B in serial1.asm
Expected bank 0 for r0x4C in serial1.asm
Expected bank 0 for r0x4D in serial1.asm
.
.
.

(I haven't touched the serial code.)

from the linker. I suspect this means that I'm using too much RAM in the PIC, but does anyone know for sure?


best wishes

Adrian

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[reprapltd.com]
Re: SDCC ignorance
June 30, 2007 01:48PM
Can't say for sure since I don't use SDCC. I do know that Microchip PIC's, even the biggest ones, have a really dinky amount of RAM and it is very easy to use it all up. I don't know why Microchip designs PICs like that.
Re: SDCC ignorance
June 30, 2007 10:43PM
Two ideas that could help test your theory:

(a) make the ring buffer one byte long -- does the linker then link without warnings?

(b) compile and link for the 16F648A -- does the linker then link without warnings?

Jonathan
Re: SDCC ignorance
July 02, 2007 07:41AM
Simon McAuliffe wrote:
> RepRap Forum Mailer wrote:
>> from the linker. I suspect this means that I'm using too much RAM in
>> the PIC, but does anyone know for sure?
>>
>
> Yep, that sounds looks about right.
>
> I was actually going to write up a description of an approach of was
> thinking of using to do this, in order to synchronise the activities of
> the various PICs involved. But I see now that I was a bit slow. You
> need some kind of synchronisation because the PIC that is sending the
> sync pulses can change without any word from the host controller, so it
> complicates things a bit. Is that something you have taken into account?

Thanks Simon - it definitely turned out to be a memory limitation, after
I tried a few experiments suggested by Jonathan.

I've got round the RAM limitation by the hacky (but kinda neat) strategy
of putting my ring buffer in the (at the moment unused) EEPROM. This is
slower than RAM, of course, but that doesn't matter for variables that
are not being accessed in a tight loop. Also SDCC doesn't touch the
EEPROM, so you have complete control over what you put in there and what
you do with it. I just hope it can survive a lot of read-write cycles...

What I've done so far is to take these lines from

case CMD_DDA:

seekPosition.bytes[0] = buffer[2];
seekPosition.bytes[1] = buffer[3];
dda_deltay.bytes[0] = buffer[4];
dda_deltay.bytes[1] = buffer[5];
setTimer(buffer[1]);

stick the buffer values as a frame in the ring in that order, and then
subsequently get them back to put the bytes into seekPosition etc.

That works (though is not yet exhaustively tested).

What I want to do next is to get it to check the buffer when it gets a
CMD_DDA and, if it's empty or has only one frame in it, add the new one.
If it was empty it will then immediately send the "I've finished that
line" sequence back to the Java; if not, not.

Then when it really has finished a line I'll get it to check the buffer
to see if there's another one waiting. If there is it'll load it into
seekPosition etc., and then send another "I've finished that line" sequence.

And so on.

Can you see any reason why that shouldn't work? In particular, I'm not
sure if it will handle the case when the first line has big delatX and
small deltaY, and the second has the opposite, because in the first case
the X controller generates the syncs, and in the second case it's the Y
(if I understand it correctly), and I'm not sure if I'm doing enough to
handle that transition.

--

Best wishes

Adrian

Dr Adrian Bowyer
[staff.bath.ac.uk]
[reprap.org]
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Re: SDCC ignorance
July 02, 2007 12:32PM
> I just hope it can survive a lot of read-write cycles...

Hmmm. That might prove to be optimistic, and if it fails, the failure could be hard to diagnose. Have you done any form of write-levelling, moving the buffer around in the EEPROM and keeping a pointer to the current copy in RAM?

I have to say, I think moving to a 16F648A is probably preferable to this sort of trickery.

Jonathan
Re: SDCC ignorance
July 02, 2007 01:49PM
Quoting RepRap Forum Mailer :

>> I just hope it can survive a lot of read-write cycles...
>
> Hmmm. That might prove to be optimistic, and if it fails, the
> failure could be hard to diagnose. Have you done any form of
> write-levelling, moving the buffer around in the EEPROM and keeping a
> pointer to the current copy in RAM?
>
> I have to say, I think moving to a 16F648A is probably preferable to
> this sort of trickery.

Probably - it's all too easy to get enthusiastic about a cunning, but
ultimately silly, workround.

Only problem is that PROCESSOR=16F648A doesn't fly with my sdcc version:

[SDCC :
mcs51/gbz80/z80/avr/ds390/pic16/pic14/TININative/xa51/ds400/hc08 2.5.4
#1183 (Jun 17 2007) (UNIX)].

I've slightly lost track of which one I should be using...

Best wishes

Adrian

Dr Adrian Bowyer
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Re: SDCC ignorance
July 02, 2007 03:17PM
On Tue, 2007-07-03 at 04:32 +1200, RepRap Forum Mailer wrote:
> Hmmm. That might prove to be optimistic, and if it fails, the failure
> could be hard to diagnose. Have you done any form of write-levelling,
> moving the buffer around in the EEPROM and keeping a pointer to the
> current copy in RAM?
>
> I have to say, I think moving to a 16F648A is probably preferable to
> this sort of trickery.

I think so too. The EEPROM in the PICs is fairly durable, but still dies
after 10,000,000 cycles.

Vik :v)

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sai
Re: SDCC ignorance
July 02, 2007 05:01PM
Adrian Bowyer wrote:
> I've got round the RAM limitation by the hacky (but kinda neat)
> strategy of putting my ring buffer in the (at the moment unused)
> EEPROM. This is slower than RAM, of course, but that doesn't matter
> for variables that are not being accessed in a tight loop. Also SDCC
> doesn't touch the EEPROM, so you have complete control over what you
> put in there and what you do with it. I just hope it can survive a
> lot of read-write cycles...

Gosh, that's a little scary. The EEPROM isn't really designed for that
kind of use smiling smiley

It is rated at 1,000,000 writes, so it might be okay. But it would
probably limit the life of a RepRap to printing perhaps a thousand parts
after which it may start to fail in weird and wonderful ways.

Is there a little space in one of the other banks? The biggest benefit
from the ring buffer is probably a buffer of size 2 (or an additional
buffer of size 1) and then diminishing returns. Presumably one entry in
the buffer is 5 bytes (does that sound right?). So just finding 5
additional bytes doesn't seem like too tall an order. It would be worth
looking at the map file to to see the actual register allocation. It
should provide some clues. If there's really nothing left, we can
probably adjust some other memory usage to free up that much. How big a
ring buffer are you hoping for?
>
> What I've done so far is to take these lines from
> [...]
> And so on.
>
> Can you see any reason why that shouldn't work? In particular, I'm
> not sure if it will handle the case when the first line has big delatX
> and small deltaY, and the second has the opposite, because in the
> first case the X controller generates the syncs, and in the second
> case it's the Y (if I understand it correctly), and I'm not sure if
> I'm doing enough to handle that transition.

Yeah, I think that's going to run into some problems for exactly that
reason. That's what I was talking about when I mentioned syncs too.

The PICs can either be in master or slave mode, where the master
generates the DDA pulse and the slave just moves in the right direction
when it gets a pulse. The master is always the one with the longest
delta. So if you start another line with the situation reversed you
also need to switch roles and the other one becomes the master.

My suggestion that I was going to run by the dev list first was to use
the second sync line to control the sync between lines. So SYNCA is
used to sync the individual steps within a line and SYNCB is used to
sync the lines themselves.

Each PIC would store in their ring buffer either the (speed, seek
position, deltay) *or* the fact they should be slave, along with the
sync mode which could perhaps be (0, seek_mode, 0) or something like
that in the same ring buffer for the sake of conserving memory. When a
master finishes its DDA process, it would strobe the SYNCB line and then
process the next action in the ring buffer, which would either cause it
to start a new DDA or become a slave. At the same time, the slave
seeing the SYNCB does the same thing, potentially becoming the master
and driving the next DDA.

The reason I didn't jump straight into doing this is [partly the fact I
didn't get around to it yet and] that I didn't want to use such a
precious resource as SYNCB without checking what people thought of it.
There's no other sync lines left after that, so we need to use it wisely.

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Re: SDCC ignorance
July 03, 2007 07:57AM
Simon McAuliffe wrote:
> Adrian Bowyer wrote:
>> I've got round the RAM limitation by the hacky (but kinda neat)
>> strategy of putting my ring buffer in the (at the moment unused)
>> EEPROM. This is slower than RAM, of course, but that doesn't matter
>...
> Gosh, that's a little scary. The EEPROM isn't really designed for that
> kind of use smiling smiley
>
> It is rated at 1,000,000 writes, so it might be okay. But it would
> probably limit the life of a RepRap to printing perhaps a thousand parts
> after which it may start to fail in weird and wonderful ways.

Yes - I thought that might be a problem, and Jonathan was rightly, if
politely, aghast at what I'd done when all I really needed to do was
reach for a PIC16F648a and use those extra 25 bytes...

I know that you were unhappy about the generated code bloat of later
SDCC versions than the one we're using. But we're not short of program
space. What do people feel about switching to the PIC16F648a and
keeping up-to-date with SDCC?

> The PICs can either be in master or slave mode, where the master
> generates the DDA pulse and the slave just moves in the right direction
> when it gets a pulse. The master is always the one with the longest
> delta. So if you start another line with the situation reversed you
> also need to switch roles and the other one becomes the master.
>
> My suggestion that I was going to run by the dev list first was to use
> the second sync line to control the sync between lines. So SYNCA is
> used to sync the individual steps within a line and SYNCB is used to
> sync the lines themselves.
>
> Each PIC would store in their ring buffer either the (speed, seek
> position, deltay) *or* the fact they should be slave, along with the
> sync mode which could perhaps be (0, seek_mode, 0) or something like
> that in the same ring buffer for the sake of conserving memory. When a
> master finishes its DDA process, it would strobe the SYNCB line and then
> process the next action in the ring buffer, which would either cause it
> to start a new DDA or become a slave. At the same time, the slave
> seeing the SYNCB does the same thing, potentially becoming the master
> and driving the next DDA.
>
> The reason I didn't jump straight into doing this is [partly the fact I
> didn't get around to it yet and] that I didn't want to use such a
> precious resource as SYNCB without checking what people thought of it.
> There's no other sync lines left after that, so we need to use it wisely.

I would like to be able to drive X, Y, and Z with a 3D DDA. I know we
don't do that at the moment, and the machine doesn't need it yet. But
it's so obviously elegant and symmetrical that we ought not to abandon
the potential to do it lightly.

But Ed is finding that the single biggest quality issue we have with
Darwin is the pause between the end of one XY line and the start of the
next, and I guess quality of what we need takes priority over symmetry
and elegance for their own sake.

--

Best wishes

Adrian

Dr Adrian Bowyer
[staff.bath.ac.uk]
[reprap.org]
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Re: SDCC ignorance
July 03, 2007 08:37AM
"But Ed is finding that the single biggest quality issue we have with
Darwin is the pause between the end of one XY line and the start of the
next..."

That's by no means just a Darwin issue. I had the same problem with Tommelise. I've got it under a lot better control now, but it's still not completely solved.
Re: SDCC ignorance
July 03, 2007 02:55PM
On Tue, 2007-07-03 at 12:59 +0100, Adrian Bowyer wrote:
> I know that you were unhappy about the generated code bloat of later
> SDCC versions than the one we're using. But we're not short of
> program
> space. What do people feel about switching to the PIC16F648a and
> keeping up-to-date with SDCC?

I don't have a problem with it. Beats scratching around in EEPROM for a
few bytes anyway!

Vik :v)

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Migration to SDCC 2.7.0 and 16F648A
July 03, 2007 04:40PM
Moving to 16F648A and current SDCC (2.7.0) is probably the right thing to do. Dependence on a specific ancient Subversion revision of SDCC is something we need to fix anyway, IMO.

This change is likely to need some time from Simon, because my earlier attempts to get the current C code to compile under a current SDCC are, umm, still incomplete (i.e. they don't work yet!), and I'm going to be time-constrained until at least early August. And I'm more comfortable with host code anyway :-)

Q1: Simon, are you willing and able to take the lead in migrating RepRap to a 16F648A and SDCC 2.7.0 ?

Q2: Does anyone know of still *more* things which will need additional PIC RAM, before RepRap 1.0 can build its own set of parts?

The 16F648A only gets us 32 bytes of extra RAM over the 16F628A (256 rather than 224) ... and that *it*! After that, I think we're looking at a redesign of the UCB for a different PIC family altogether, probably something from the 18F family.

Therefore, if we can forsee any need for more RAM than a 16F648A has, prior to RepRap Darwin 1.0 release, then let's not even go to the 16F648A, let's just bite the bullet and migrate all the way up to a chip with Kbytes of RAM! I know we're all hoping to delay that kind of major change until v2.x, but migrating twice (to 16F648A and then to 18Fxxxx) within a few short months because we didn't think quite far enough ahead would be... decidedly frustrating!

Jonathan
sai
Re: Migration to SDCC 2.7.0 and 16F648A
July 03, 2007 04:48PM
jmarsden wrote:
> Q1: Simon, are you willing and able to take the lead in migrating RepRap to a 16F648A and SDCC 2.7.0 ?
>

I've already done it. Not very well tested though.

> Q2: Does anyone know of still *more* things which will need additional PIC RAM, before RepRap 1.0 can build its own set of parts?
>

The improved comms system uses more RAM, but so much so that it really
needs to wait until we move up to a new chip family.

> The 16F648A only gets us 32 bytes of extra RAM over the 16F628A (256 rather than 224) ... and that *it*! After that, I think we're looking at a redesign of the UCB for a different PIC family altogether, probably something from the 18F family.
>

Plus extra ROM. It's still real tight though with new versions of sdcc.

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Re: Migration to SDCC 2.7.0 and 16F648A
July 03, 2007 05:31PM
sai wrote:

>> Q1: Simon, are you willing and able to take the
>> lead in migrating RepRap to a 16F648A and SDCC 2.7.0 ?

> I've already done it. Not very well tested though.

Great! Should we start a new branch in Subversion for this, until it has had more testing and can then be made "official"... or (once we have something approaching consensus) should we just just do it in the trunk?

>> Q2: Does anyone know of still *more* things which will need
>> additional PIC RAM, before RepRap 1.0 can build its own set of parts?

> The improved comms system uses more RAM, but so much so that it really
> needs to wait until we move up to a new chip family.

OK. Is there anything we gain from the improved comms system that is likely to be necessary (as opposed to "nice to have if we can get it") for Darwin 1.0? BTW, is there a description of the new comms system and its features and benefits somewhere, for the rest of us to read?

Jonathan
Re: Migration to SDCC 2.7.0 and 16F648A
July 04, 2007 06:04AM
Simon McAuliffe wrote:
> jmarsden wrote:
>> Q1: Simon, are you willing and able to take the lead in migrating
>> RepRap to a 16F648A and SDCC 2.7.0 ?
>>
>
> I've already done it. Not very well tested though.
>
>> Q2: Does anyone know of still *more* things which will need
>> additional PIC RAM, before RepRap 1.0 can build its own set of
>> parts?

We can plug it into Darwin and test it quite easily, so let's go for that.

> The improved comms system uses more RAM, but so much so that it
> really needs to wait until we move up to a new chip family.
>
>> The 16F648A only gets us 32 bytes of extra RAM over the 16F628A
>> (256 rather than 224) ... and that *it*! After that, I think we're
>> looking at a redesign of the UCB for a different PIC family
>> altogether, probably something from the 18F family.
>>
>
> Plus extra ROM. It's still real tight though with new versions of
> sdcc.

Is that the existing code being really tight, or the new comms code? If
the former we are in trouble. If the latter, not so bad.

>> The improved comms system uses more RAM, but so much so that it
>> really needs to wait until we move up to a new chip family.
>
> OK. Is there anything we gain from the improved comms system that is
> likely to be necessary (as opposed to "nice to have if we can get
> it") for Darwin 1.0?

The remaining problems that I know of are:

1. The pause-between-lines problem. 32 bytes are easily enough to fix
that I think. I am more worried about the need to use the extra sync
line too, as that stops us generalising 3D movements. Maybe we should
leave that for Mendel.

2. Comms errors. These seem benign except in one place - when they
happen during a cooling cycle. That then gets extended about threefold
while it waits then gives up. Annoying, but not a disaster. Leave the
new comms code for Mendel too?

To summarise -

For Darwin: I propose we should switch to 16F648A/SDCC-2.7.0 and fix the
pause problem. Leave the comms imperfect, but workable.

For Mendel: we switch to 18Fx, redesign the UCB, use Simon's new comms
code, and make the DDA work in 3D rather than 2.

What do people think? In particular is there any killer problem that I
have missed?

--

Best wishes

Adrian

Dr Adrian Bowyer
[staff.bath.ac.uk]
[reprap.org]
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Re: Migration to SDCC 2.7.0 and 16F648A
July 04, 2007 06:24AM
On Wed, 2007-07-04 at 11:05 +0100, Adrian Bowyer wrote:
> To summarise -
>
> For Darwin: I propose we should switch to 16F648A/SDCC-2.7.0 and fix
> the
> pause problem. Leave the comms imperfect, but workable.
>
> For Mendel: we switch to 18Fx, redesign the UCB, use Simon's new
> comms
> code, and make the DDA work in 3D rather than 2.
>
> What do people think? In particular is there any killer problem that
> I
> have missed?

For Mendel we'll be using servos, right? If so, can we get away without
using the L298N and do a simple H-bridge instead?

Vik :v)

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Re: Migration to SDCC 2.7.0 and 16F648A
July 04, 2007 06:35AM
Vik Olliver wrote:

> For Mendel we'll be using servos, right? If so, can we get away without
> using the L298N and do a simple H-bridge instead?

Yes - plus the odd power transistor for the cooling fan etc.

--

Best wishes

Adrian

Dr Adrian Bowyer
[staff.bath.ac.uk]
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